Keynote Speakers
KRSTE ASANOVIC
Chairman at RISC-V Foundation
Presentation
RISC-V: The Next Ten Years
RICK O'CONNOR
President & CEO at OpenHW Group
Presentation
CORE-V: Industrial Grade Open Source RISC-V Cores
ANN MUTSCHLER
Executive Editor/EDA at Semiconductor Engineering
Presentation
Is RISC-V Verification Ecosystem Ready for the Coming Innovation Tsunami?
Is RISC-V Verification Ecosystem Ready for the Coming Innovation Tsunami?
SIMON DAVIDMANN
President & CEO at Imperas Software Ltd
Presentation
Is RISC-V Verification Ecosystem Ready for the Coming Innovation Tsunami?
Is RISC-V Verification Ecosystem Ready for the Coming Innovation Tsunami?
STEVE RICHMOND
Design Verification Manager for the Central R&D Division at Silicon Labs
Presentation
Is RISC-V Verification Ecosystem Ready for the Coming Innovation Tsunami?
Is RISC-V Verification Ecosystem Ready for the Coming Innovation Tsunami?
MIKE THOMPSON
Director of Verification Engineering at OpenHW Group
Presentation
Is RISC-V Verification Ecosystem Ready for the Coming Innovation Tsunami?
Is RISC-V Verification Ecosystem Ready for the Coming Innovation Tsunami?
NASR ULLAH
Senior Director, Performance Architecture at SiFive
Presentation
Is RISC-V Verification Ecosystem Ready for the Coming Innovation Tsunami?
Is RISC-V Verification Ecosystem Ready for the Coming Innovation Tsunami?
NITIN DAHAD
Editor-in-Chief at embedded.com
Presentation
Fireside Chat
DAVID PATTERSON
Vice Chair at RISC-V International
Presentation
Fireside Chat
CHRIS LATTNER
President, Product and Engineering at SiFive
Presentation
Fireside Chat
Tech Talks
Tech Talk with Lampro Mellon: An Open-Source Solution for Accelerating Verification of RISC-V Processors
Within the domain of SoC design and verification, LM has created RISC-V DV that combines RISCV-DV test generator, Spike ISS, and SweRV core into a seamless end-to-end flow — from random assembly test generation and RTL compilation to post-simulation comparison. This environment reduces the design cycle times and cost.
Tech Talk with SiFive: SiFive RISC-V Core IP Products
In this tech talk you will learn about Sifive’s RISC-V IP product portfolio including recent updates made to existing products as well as new product updates and supporting SiFive Shield security IP and SiFive Insight trace and debug IP.
Tech Talk with Lauterbach: Debug and Trace of RISC-V based SOC
Overview of capabilities available to debug and trace heterogeneous SOC incorporating RISC-V and other processors
Tech Talk with GigaDevice: GD32VF103 A RISC-V based MCU
Overview of the GD32VF103 including the current ecosystem.
Tech Talk with SmartDV: SmartDV’s RISC-V Solutions
Presents an overview of SmartDV’s solutions to aid the RISC-V based design and verification. The session talks about SmartDV’s currently available RISC-V CPU verification solution and TileLink Verification IPs.
Tech Talk with Antmicro: Building your world out of blocks with Renode and LiteX
This talk will present modern methods of system development based on modular open source solutions, such as Antmicro’s simulation framework Renode and the soft SoC generator LiteX.
Tech Talk with Secure-IC: Overview of Secure-IC Solutions to Secure RISC-V Core
In this short talk, we will present Secure-IC company and solutions to secure RISC-V cores. Our solutions are named the Cyber Escort Unit and the Securyzr. The Cyber Escort Unit is a Cyber Security add-on for processor. The Securyzr is an integrated Secure Element used to offer multiple services, such as Secure Boot, for the core.
Tech Talk with Cobham Gaisler: The Case for RISC-V in Space Applications
Why do the providers of the fault-tolerant LEON/SPARC architecture believe that RISC-V will be dominating space in the future?
Tech Talk with OpenHW Group: CORE-V Verification Test Bench
In this session, we will briefly introduce the OpenHW Group and its top-down approach to verification. A primary goal of this Tech Talk to is motivate Summit participants to attend the hour-long tutorial session on Thursday will delve into the details of the simulation and formal verification applied to the CV32E40P project.
Tech Talk with Seagate: Data on the Move: A RISC-V Opportunity
With the predicted explosion of data over the coming decade, Seagate is investing in novel solutions to enable data protection, movement, and storage. As an active participant in the RISC-V community, Seagate sees the RISC-V open ISA as central to solving these data challenges. Seagate will present domain-specific use cases, status of processor development, and a vision for future applications.
Tech Talk with Cobham Gaisler: The Case for RISC-V in Space Applications
Why do the providers of the fault-tolerant LEON/SPARC architecture believe that RISC-V will be dominating space in the future?
Time's running out!
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JOIN US AT RISC-V SUMMIT 2020 December 8–10
Use promo code LAMPROMELLON to save 25% on registration
